Hi there. I'm an analog electronics design engineer at EADS Astrium in the UK.
I work alongside digital hardware designers and software developers covering aerospace applications. Max (our illustrious editor in chief here at All Programmable Planet) told me that many FPGA designers could do with a little help understanding how to interface the analog world to their digital domain. Eventually, I could no longer find the strength to struggle against Max's pitiful pleadings and I agreed to explain the wibbly-wobbly analog world in ways that even he could understand (his words, not mine). So here we go...
Many transducers, such as electrochemical gas sensors, for example, produce very low-level signals. Depending upon the transducer in question, the signal can be a voltage, or a current, or even a varying electrical resistance. When I say "low-level," I'm talking about values such as 41μV per degree Celsius from a thermocouple or 10nA per "unit" from an electrochemical sensor. The point is that it is not viable or desirable to apply such signals to an analog-to-digital converter (ADC) without first using an intermediate analog signal amplification stage.
While some applications use digital methods to filter out noise from an analog signal after analog-to-digital (A/D) data conversion has been performed, there is another problem with analog signal amplification -- DC voltage offset errors. Not only do such errors add to, or subtract from, the analog signal of interest, but they may also drift with respect to temperature, time, and power supply voltage variations. Unlike noise signals, these are DC drift errors. They pose a significant problem when attempting to amplify the analog signal, because the amplifier must allow the desired DC signal through, which means it cannot block DC drift from influencing the signal of interest.
Let's consider a very high-level view of the signal path as it makes its way from some form of transducer/sensor, through an amplifier block, into an ADC, and eventually -- in digital form -- into an FPGA:
Now, the first thing Max asked me when he saw this diagram was "Why do we have to have multiple amplification stages in the DC and AC amplifier block -- canít we simply use a single amplifier?" Well, I will be covering all of this in more detail in future blogs, but -- for the purposes of this column -- I can summarize things in a (simplified) nutshell as follows: If you have an amplifier with a voltage gain of 1 and a bandwidth of 100MHz, then using the same amplifier with a voltage gain of 10 reduces the bandwidth to 10MHz. That is, multiplying the voltage gain by some value "X" means the available bandwidth is divided by the same value "X." Thus, if we were to use the same amplifier with the voltage gain set to 100, this would reduce the bandwidth to only 1MHz. However, if we were to use two of these amplifiers in series, both with their voltage gains set to 10, then we would retain a bandwidth of 10MHz while achieving a total voltage gain of 10 x 10 = 100 (ta-dah!).
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