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Max Maxfield
Max Maxfield
5/23/2012 10:45:05 AM
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Re: Other hard devices
With regard to having analog stuff in FPGAs like analog-to-digital converters (ADCs), the latest 7 Series FPGAs from Xilinx include something called Agile Mixed Signal (AMS) technology, which provides anything from simple analog monitoring (that can be used for voltage, current, temperature monitoring functions for board and platform management) to more complex analog signal processing, resulting in lower system cost, smaller area, and increased reliability.

With regard to real-time clock and calendar (RTCC) functions -- I guess you could create these as soft macros, but some FPGAs (like the Zynq EPP from Xilinx) include hard dual core ARM Cortex-A9 Microcontroller subsystems, which themselves include hard real time counter/timers

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mgburr
mgburr
5/23/2012 9:03:06 AM
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Beginner
Re: Other hard devices
I like the idea of High Gate Count to low Pin count, but I wonder if in doing so it wouldn't also limit the capabilities.  I suppose adding a dedicated "mote" area to the outside so you can still create the data paths for the higher count to funnel down.  I suspect the biggest reason we don't see them is the cost per gate as it aggregates out to the pins.  in effect the hgher gate count could make certain areas of the Silicon inaccessable if you reduced the number of accessable pins from the outside.  I think it would be a waste to have the gates there and not accessable.  Although I'm pretty sure some entrprising young British Engineer is working on that :-) 

 

 

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Paul Clarke
Paul Clarke
5/23/2012 8:38:02 AM
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Other hard devices
So with referance to having a hard core in a FPGA we also have PLLs SRAM etc all what you might consider hard elements.

I wondered if other hard elements are avalible in FPGAs like ADCs or DACs or RTCCs etc. Just seams to me that FPGAs are great but all the digital I/O ends up talking to devices like these.

Maybe there is room in the market for embeded FPGAs like when we started moving from microprocessors to microcontrollers?

Wouild also like to see more small footprint FPGAs with high gate counts, like 250k gates in a 28pin SOIC. lots of grunt in a small package.

P :o)

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