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Karl
Karl
6/5/2012 11:04:31 AM
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Re: Recollections
Hi, Jason. The answer wherever I read it  is close together.  My reasoning is timing. The first register may be metastable for some period of time, but probably less than the clock period.  We want to get the resolved state to the second register as quickly as possible so the closer the better.

At first I thought far apart to leave time for the condition to resolve -- absolutely qrong as I see it now.

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Jason Teo
Jason Teo
6/5/2012 10:48:23 AM
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Re: Recollections
Karl, you got me on this one. Restricting the discussion to FPGA, the sizing of hte register is not a consideration. Invariably, the parameters that I could think of (impedance and capacitance) between a second register that is far away and another that is near have to relate in some way to time. What is your take?

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Karl
Karl
6/5/2012 10:19:06 AM
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Re: Recollections
@Jason Given that the propagation delay time is not a factor, then what would be your reasoning?

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Jason Teo
Jason Teo
6/4/2012 9:54:35 PM
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Re: Recollections
Hi Karl, interesting question. I believe the two registers should be placed closed together, at least close enough that it has more than sufficient time to meet any timing violations. If the second register is placed far away, hypothetically more than a clock period of propagation time is needed for the signal to travel, then the second register is essentially useless to improve the metastability issue. That is my take which might be wrong.

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Karl
Karl
6/4/2012 11:56:45 AM
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Re: Recollections
Jason, the double register reduces the probability that metastab will occur since there is no way to know how long the first register can remain in meta state.

Here i a fun question: Should the two registers of the synchronizer be placed close together or far apart?

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Jason Teo
Jason Teo
6/4/2012 11:14:54 AM
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Re: Recollections
Hi Karl, interestingly, I also remembered one about metastability and how to solve it using the FPGA. This question was posted to me in a job interview. The hiring manager puts it across "There's a button that drives the input of a register. Depending on when the button is pressed, metastability as a result of timing violations could result in random output which would be used in later stages with disastrous consequences. How to fix it?" The solution is simply to register the output signal again. From digital perspective, there is not so much physics involved.

That is the beauty and perhaps short-coming of the digital world. To all the readers, I must disclaim that I meant it in the general sense based on the my limited experiences. If you disagree, please educate me.

Karl, please keep those recollections coming. These are fantastic stuff.

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Max Maxfield
Max Maxfield
6/3/2012 10:12:34 PM
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Re: Recollections
@Sven: The Computer History Museum is a must see. When Konraz Zuse was inducted to their hall of fame a few years ago, his son - Horst Zuse - invited me to attend ... very impressive.

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David Ashton
David Ashton
6/3/2012 8:03:37 PM
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Guru
Re: Recollections
@Karl...am trying to avoid this getting too thin so hope it comes in the right place.  Some time ago on EE Times there was an article on the first video game:

http://www.eetimes.com/electronics-blogs/other/4211525/One-of-the-first-video-games-makes-a-comeback

Be sure to look at the link which has a video:

http://scienceblogs.com/brookhaven/2010/12/14/resurrecting-one-of-the-worlds/

Fascinating stuff for analogue devotees....bit off the subject of programmable logic but this is a column about recollections.  An FPGA could do much the same thing (might need a DAC or two, but you could probably do a digital video output) and keep score and a high-scorer's list as well....

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Karl
Karl
6/3/2012 11:11:27 AM
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Guru
Re: Recollections
Hi, Jason -- just remembered one about metastability.  I think it was the first time it was observed.

There was a multiprocessor being designed that had IO channels that did DMA and of course there had to be an arbiter to determine priority to access memory. The requests were asynchronous so just as access was being granted to one channel, a higher priority request could arrive and block the grant.  The first grant would become a very narrow pulse and sometimes cause a latch to go metastable.

No one knew about metastability until a circuit design engineer set up an experiment with a scope on the latch output and a way to adjust the input pulse width.  Sometimes it would oscillate for a while, sometimes it would hover at about the triggering threshhold, of course sometimes stabilize normally.

The conclusion was that the cross coupled circuits that formed the latch would reach a "unity gain" point where each circuit would drive the other just to the switching threshhold and stay there until noise or something random disturbed the equilibrium.  The scope images were dubbed "rooster tails" or oscillations.

The fix was to redesign the latch so it would not reach unity gain.  No, I don't know how it was done, but on a couple of other occasions the same engineer came up with circuits that solved metastability problems.

Of course that was before integrated circuits where it is not possible to modify the circuitry.

 

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Karl
Karl
6/3/2012 10:29:33 AM
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Guru
Re: Recollections
David, I took  a course in 1963 and may still have the text book.  My lowest grade was that course, too.  Analogs with opamps and RC networks can do really interesting things and get continuous solutions -- like aiming a gun at where an airplane is going to be at the time the projectile gets there.  A planned collision.

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