Niki
6/18/2012 6:17:34 PM
User Rank Beginner
Re: Port / Signal naming conventions
@Max: Sorry it took so long, but here is a simple example. It is a simple synchronous FIFO. I took out the overflow/underflow logic to make it simpler. It does not contain all elements of my little convention but gives the general idea. In any case, for what it is worth!
The file is located at the following URL: https://docs.google.com/open?id=0B8SYtouT8_ClNEZtM3ktbjdwNkk
--------------------------------------------------------------------------
-- Description : Implement a simple synchronous FIFO. Input and output
-- ports have equal width (determined by DATA_WIDTH)
-- while the depth is determined by DEPTH, and must
-- be a power of 2. Output is transparent not registered.
-- Over and underflow are NOT detected and must be avoided
-- by design. Simultaneous read and write is allowed.
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity SyncFifo is
generic ( DATA_WIDTH : integer := 8;
DEPTH : integer := 4); -- Must be a power of 2!
port (
-- Global clock and reset
pClk : in std_logic;
pnReset : in std_logic;
-- Data input signals
-- Input data bus
pDataIn : in std_logic_vector (DATA_WIDTH-1 downto 0);
pWrEnable : in std_logic;
pFifoFull : out std_logic;
-- Data output signals
-- Output data bus
pDataOut : out std_logic_vector (DATA_WIDTH-1 downto 0);
-- Indicate that output data has been used
pRdEnable : in std_logic;
pFifoEmpty : out std_logic
);
end SyncFifo;
architecture SyncFifo_Arc of SyncFifo is
-- Fifo memory (registers)
type tFifoMem is array (DEPTH-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal sFifoMem : tFifoMem;
-- Fifo flags and indices.
signal sFifoFull, sFifoEmpty : std_logic;
signal sWrIndex, sRdIndex : integer range DEPTH-1 downto 0;
signal sFifoLevel : integer range DEPTH downto 0;
begin
-- Process to control reading and writing indexes and FIFO level.
-- Generally writing causes sWrIndex and sFifoLevel to be incremented,
-- while reading causes sRdIndex incremented and sFifoLevel to be decremented.
-- Simultaneous reading and writing increments both indexes, but leaves
-- sFifoLevel unchanged.
-- Undeflow and overflow NOT detected/prevented.
FifoRdWr:process (pClk, pnReset)
begin
if pnReset = '0' then
sRdIndex <= 0;
sWrIndex <= 0;
sFifoLevel <= 0;
for i in 0 to DEPTH-1 loop
sFifoMem(i) <= (others => '0');
end loop;
elsif pClk'event and pClk = '1' then
if pRdEnable = '1' then
sRdIndex <= (sRdIndex+1) mod DEPTH;
-- Adjust FIFO level if a write is not also in progress.
if pWrEnable = '0' then
sFifoLevel <= sFifoLevel - 1;
end if;
end if;
if pWrEnable = '1' then
-- Write data into FIFO
sFifoMem(sWrIndex) <= pDataIn;
-- Increment index
sWrIndex <= (sWrIndex+1) mod DEPTH;
-- Adjust FIFO level if a read is not also in progress.
if pRdEnable = '0' then
sFifoLevel <= sFifoLevel + 1;
end if;
end if;
end if;
end process;
-- Process to create FIFO Full and FIFO empty flags.
FifoFlags:process (pClk, pnReset)
begin
if pnReset = '0' then
sFifoFull <= '0';
-- The FIFO starts up empty.
sFifoEmpty <= '1';
elsif pClk'event and pClk = '1' then
if pWrEnable = '1' and pRdEnable = '0' and sFifoLevel = DEPTH-1 then
sFIFOFull <= '1';
elsif pWrEnable = '0' and pRdEnable = '1' then
-- Not simultaneous read and write
sFIFOFull <= '0';
end if;
if pRdEnable = '1' and pWrEnable = '0' and sFifoLevel = 1 then
sFIFOEmpty <= '1';
elsif pWrEnable = '1' then
sFIFOEmpty <= '0';
end if;
end if;
end process;
-- The data output of the FIFO is simply the slot pointed to by
-- sRdIndex (output is not registered)
pDataOut <= sFifoMem(sRdIndex);
pFIFOFull <= sFIFOFull;
pFIFOEmpty <= sFIFOEmpty;
end SyncFifo_Arc;
Brian
6/13/2012 7:21:04 PM
User Rank Guru
Re: Port / Signal naming conventions
@Niki: Thanks much!
Niki
6/13/2012 6:45:37 PM
User Rank Beginner
Re: Port / Signal naming conventions
@Brian: No problem - I have uploaded a picture ;-)
@Max: Will post an example tomorrow.
Brian
6/11/2012 1:56:45 PM
User Rank Guru
Re: Port / Signal naming conventions
@Niki: Thank you for all of these comments/posts. Your ideas and suggestions are excellent.
However and on another note, please consider uploading an image in your profile.
See article and comment chain, here. :-)
By the way, you are not being 'picked on' - we want everyone to upload a unique image so we can quickly recognize the person's comments from their historical comments... And, we sure hope that you keep commenting! Thanks.
Re: Port / Signal naming conventions
Hi Niki -- I really like all of this -- how about you throw together a small routine -- say 20 lines of code -- maybe show it with keywords uppercase and user-defined signals, ports, and variables (a) lowercase and (b) without your convention. And then do the same thing but with the signals, ports, and variabled defined using your convention.
I can either post this as a blog of just upload it as a file people can download and look at (or both) -- that would really help them see what we are talking about.
Niki
6/11/2012 9:59:54 AM
User Rank Beginner
Re: Port / Signal naming conventions
:-)
There is one more element in my little convention which I fogot to mention: I also prepend a lower case 'n' for an active low signal / port. E.g. snWrite or pnEnable. It is then immediately clear what the active level is. Lastly, although I also try to avoid using too many variables, I prepend a 'v' to any variable. Again, it is immediately clear in the process that you are working with a variable (although the := instead of <= also indicates this).
So, in summary, I have three "object type indicators": 's', 'p' and 'v' for signals, ports and variables repectively. This is optionally followed by 'n' for active low. The first letter of the actual identifier name is upper case, which neatly delimits the prefixes. Fairly light weight, but it adds significantly to code clarity. Fits the the 80/20 rule for me!
I firmly believe that debugging starts even before you start coding and that clear and concise coding reduces future debugging effort significantly.
Re: Port / Signal naming conventions
@Nike: "...blindfolded with my hands tied behind my back..."
Now that's a talent they just don't teach at university anymore (grin)
Niki
6/11/2012 4:18:29 AM
User Rank Beginner
Re: Port / Signal naming conventions
@Max - it does become second nature, to the point where you do not even 'see' the 's' or the 'p' anymore. I can type:
process (pClk, pReset)
begin
if pReset = '1' then
elsif pClk'event and pClk = '1' then
end if;
end process;
blindfolded with my hands tied behind my back ;-)
Re: Port / Signal naming conventions
@Niki -- thanks so much for this -- I really like this way of doing things -- it may be a tad more work when you first start coding thsi way, but it will soon become second nature -- and it will certainly help with understanding the code at a later date. It's a little similar to that scripting example I gave early on in these comments, but with the addition of s for signal and p for port ...
ravi
6/9/2012 1:05:30 PM
User Rank Clever Clogs
Re: VHDL Coding Standards document
@Adam Thanks a lot Adam. Appreciate the clarification.
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