eteam00
9/29/2012 5:27:28 PM
User Rank Guru
updated diagram
Adam,
I suggest a slight modification to your excellent waveform diagram. The "NEW" label should be moved rightward to the light blue section of the waveforms. This reflects the normal application of a transparent latch, while demonstrating all the points you make in your blog posting.
- The latch normally opens before 'valid data' arrives at the input.
- Valid input normally flows through the latch while latch is open
- The latch normally closes while input data is still 'valid', extending the 'valid' time of the latch output.
Here is your diagram, with minor changes applied:
I like your colour coding -- it's a nice touch that definitely improves readability.
-- Bob Elkind
Re: Great explanation
@Celine: Make sure you check out Adam's 2-part article on Metastability in registers and latches http://bit.ly/NiNTUZ and http://bit.ly/MdlQXF (also note that the second part has two pages so you have to click the "more" link)
celine
7/9/2012 4:01:49 AM
User Rank Expert
Great explanation
Thank you for this synthesis, I finally can get together the little pieces of knowledge that I had about the subject in a whole that makes sense. And I now really understand why I always avoided latches in my designs.
I forward the link for my fellow coworkers that intend to begin with FPGA !
Re: good topic
@Thrakkor -- thanks for uploading a picture for your profile -- and it's a great picture by the way
Re: good topic
I would imagine that most FPGA's consist of stages like this, i.e. enabled registers as you say a similar name would be enabled register as opposed to synchronous latch.
Every FPGA engineer should avoid latches I would hope, although I am sure our newer FPGA designers will inadvertantly create a few hence the blog attempting to explain what causes them and why they are not recommmended.
Re: good topic
@Thrakkor: Good point -- Adam is in the UK and has gone home for the weekend, but I'm sure he will answer this over the weekend...
thrakkor
6/8/2012 10:58:57 AM
User Rank Blogger
good topic
its probably unintentional, but the synchronous process figure description indicates it is a 'synchronous latch', but IMO, a less confusing description would be a register that only updates when enabled.
I personaly use stages like this whenever I am pipelining data with a valid strobe. I also use a variation of these regularly in single process FSMs (i.e., no default or else conditional).
I avoid latches like the plague myself.
robbiev
6/8/2012 7:30:53 AM
User Rank Beginner
Nice job
Indeed nice, can't wait for next blogpost :-)
Brian
6/8/2012 12:04:14 AM
User Rank Guru
Re: Love the Graphics!!!
@Max: Re: "a man of hidden talents!"
They aren't hidden - he put them out there for the world to see! :-)
Adam - that was a good read. I liked seeing the text, figures and code all together - very easy to follow. Nice job!
Re: Love the Graphics!!!
No just a great editor ;)
Just got the LX9 board up and running beat going to bed (23:30) here
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