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Max Maxfield
Max Maxfield
7/17/2012 11:16:00 AM
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Way Cool!
Hi Adam -- thanks for this -- I have to admit that I've always found the whole concept of virtual logic analyzers to be WAY COOL!!! (grin)

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Adam Taylor
Adam Taylor
7/17/2012 11:19:33 AM
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Re: Way Cool!
@max I agree they are very cool, I first ran into them about 10 years ago at Raytheon and they allowed me to do some verification in a development board before we even saw hardware. Provided you have the free memory blocks then they are very good and easy to use also

 

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Brian
Brian
7/17/2012 12:21:35 PM
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Guru
Re: Way Cool!
 

@ Max, Adam: This is cool, thanks for posting!

Besides the reasons you mention in the blog (limited I/O, logic analyzer sharing, real estate for test header, etc.), I think another benefit is cost-savings.  Logic Analyzers are expensive (hence, the sharing w/other project teams)!

So, this idea would be a perfect solution for DIYers and hobbyists that otherwise might avoid FPGA's because they don't have the lab/debug tools available.

 

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Max Maxfield
Max Maxfield
7/17/2012 1:10:51 PM
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Re: Way Cool!
@Brian: That's a good point -- also in larger FPGAs with more resources you could have a whole bunch of these monitoring different signals just waiting for that "unexpected" event to occur...

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Max Maxfield
Max Maxfield
7/17/2012 1:13:53 PM
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Re: Way Cool!
I guess we should note that some FPGA designs are logic limited, in which case you might be pushed to squeeze even one virtual logic analyzer in.

Having said this, a lot of FPGA designs are I/O limited -- by which I mean they are straining the I/O resources but have logic capacity to spare -- these are ideal candidates for deploying virtual logic analyzers...

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Adam Taylor
Adam Taylor
7/17/2012 3:02:36 PM
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Re: Way Cool!
Indeed these and the ipad logic analysers make it very easy for hobbyist's. I have recently been talking with Ian (http://www.programmableplanet.com/messages.asp?piddl_msgthreadid=252298&piddl_msgid=712103#msg_712103) about his idea for a hobbyists VHDL course I think he is firming up on the details of it now. His site is fpga-design-solutions  

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Adam Taylor
Adam Taylor
7/17/2012 3:05:20 PM
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Re: Way Cool!
@max you can also take in to account the requirements for logic utilisation we typically aim to occupy only 80% of the deign to provide room for extra additions which might be required later on in the development process. 

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AndySlimming
AndySlimming
7/17/2012 3:16:02 PM
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Beginner
Virtual logic analyser
I have used ChipScope to debug designs. It is very usefull for recording input data to your design which you can then playback through your logic simulation where you can monitor all the nodes in your design and work out why a problem is happening.

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Max Maxfield
Max Maxfield
7/17/2012 3:18:30 PM
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Re: Way Cool!
@Adam: Good point -- these are the sort of points that are really useful for newcomers to FPGAs to be made aware of -- it's like when you see a professional plumber or tiler or carpet layer or cabinet installer .. they have all sorts of tricks that they use to make things go faster and guive better results that you would never think of if you were doing it yourself for the first time...

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Adam Taylor
Adam Taylor
7/17/2012 3:21:16 PM
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Re: Way Cool!
The other thing to realise it is hard to get FPGA to run at speed if they are fully utilised. Vendors might claim differently though 

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