Re: Duane can use ChipScope (hurray!)
@Bummer re ChipScope, but I like the CheapScope idea because everyone can use it...
Re: Duane can use ChipScope (hurray!)
Max - I contacted Xilinx support and after a few emails back and firth, they directed me to Avenex whom I haven't heard back from yet. I think this will be a good opportunity to check out Hamster's CheapScope.
Re: Duane can use ChipScope (hurray!)
@Duane: How strange. OK, so are you calling them? Also, will you be trying Hamster's CheapScope?
Re: Duane can use ChipScope (hurray!)
Max - re LX9 and ChipScope: The web site says that it does come with that license, but alas, my computer doesn't know that. I'm stopped by a license error at the moment. Hopefully a call or email to tech support will take care of that get get me back on the road quickly.
hamster
8/7/2012 5:42:05 PM
User Rank Blogger
For those of us who arn't licensed for Chipscope.
If you aren't licesned for Chipscope, or your board doesn't have support for JTAG debugging, or you don't have a JTAG programmer I've created "CheapScope"
http://hamsterworks.co.nz/mediawiki/index.php/CheapScope
A 16 channel Virtual Logic Analyzer - the project's tagline will be "None of the features, none of the price, all on one web page".
I'm just polishing some rough edges off of it, but it is on track to take approx one pin, a smidge over 100 Spartan 3E slices and one BRAM block.
grilialex
7/30/2012 3:04:50 AM
User Rank Clever Clogs
Re: ChipScope In-Chip FPGA Virtual Logic Analyzer
Back in 2002 i persuaded our startup company to use Chipscope. We have bought a traditional PC based logic analyzer (Agilent, LA1690) as we did not have a big budget. Our design had about 2M gates splited on two virtex XCV2000.
The problem with the standard LA was that the probes disrupted electrically the signals (another aspect of using physical device), and we were afraid that maybe our instrumentation could affect our timing (imagine an 80MHz clock distorted a little by the LA's capacitance). Add up that we had many signals to observe and soon the LA was sitting in the bench idle, after resolving the first issues.
In the mean time our VHDL engineer used Chipscope. The good thing was (from what i remember) that it attaches on the Netlist. So we didn't need to resynthesize the design in order to change signals, which would need a few hours more (for the synthesis phase).Through the JTAG interface we could capture the signals we needed. We even had testbenches to compare results with Matlab.
I have a good knowldege of Logic Analyzers and i have used them extensively in the past. The disadvantages of Chipscope is the limited triggering capabilities, its memory depth, and of course that it uses logic resources in your device. From my experience though i believe that these are not a big problem when doing hardware engineering.
Cheers,
Ilias
Re: ChipScope In-Chip FPGA Virtual Logic Analyzer
Hi,
I thought we have to use to 2x the frequency to effectively sample signals in Chipscope Pro; which now appears to be wrong.Thanks for correcting this thrakkor
but i don't think using 2x the frequency to sample will cause a timing issue. ofcourse it will eat up your BRAM other than that i don't see any issue given that you generate the 2x clock from DCM.
Re: ChipScope In-Chip FPGA Virtual Logic Analyzer
Indeed the clock in the same domain as the signal is the best.
thrakkor
7/24/2012 10:20:26 AM
User Rank Blogger
Re: ChipScope In-Chip FPGA Virtual Logic Analyzer
no, actually you should use the same clock for the ILA as the logic you are capturing. if you have multiple clock domains, drop down multiple ILA cores. looking at signals in other clock domains gives unpredictable results at best. another option is to synchronize signals from other domains prior to feeding into the ILA core.
all the ILA is doing is synchronously buffering the trigger/data signals in a BRAM using the clock you feed it. not any different than if you were writing data to a FIFO or BRAM.
it doesn't have a timing mode like a traditional logic analyzer.
and trying to generate a 2x clock could potentially cause you timing closure issues.
ChipScope In-Chip FPGA Virtual Logic Analyzer
Hi Adam,
Thanks for coming up with details for a great tool like chipscope (I have not used any other Embedded LA tools). I am a person who had used chipscope in both Xilinx ISE and EDK. Has helped me and my team to debug lot of things out on the hardware.
For the newbies: If you are using the Chipscope; it needs a clock to sample all the internal signals of the design. So as per the Sampling theorem; This clock signal should be atleast twice your design frequency to sample the Internal signals effectively.
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