echen
8/17/2012 1:12:39 PM
User Rank Beginner
Re: This is true 3D-IC integration
Hi max,
Very interesting. But is there any conflit with SOItec patent?
Regards
Eddy
Re: This is true 3D-IC integration
@torki: Very interesting -- I will have to check them out :-)
Re: 1um BEOL thickness ?
@torki: Great -- thanks for this input -- for my paper I was just trying to give a "feel" for it all -- but it's nice to know I was so close -- and if I ever give a talk about this technology, will all of the info provided by everyone's feedback I will be able to nail the numbers :-)
torki
8/2/2012 5:12:32 AM
User Rank Beginner
Re: This is true 3D-IC integration
SmartCut process is pattented and owned by SOITEC. This process exists since about 15 years. (US Patent 5882987)
Look at the animation at :
http://www.soitec.com/en/technologies/smart-cut/
Smart Stacking is pattented and owned by SOITEC. It is similar to what you are drawing.
http://www.soitec.com/en/technologies/smart-stacking/
torki
8/2/2012 5:02:02 AM
User Rank Beginner
Re: 1um BEOL thickness ?
Hi Mark,
Yes a range of 1um or 2um works.
At 28nm Mx (1 to 6) stack is about 6 times 180nm (metal and via).
So this is indeed 1.08 micron.
The mid-thick metal is 400nm (metal and via)
The thick metal is 1480nm (metal and via)
Regards,
Re: 1um BEOL thickness ?
@Brian C: Sometimes I amaze even myself (grin)
Seriously, thanks for rooting this information out and sharing it with us.
Brian C.
7/30/2012 3:11:16 PM
User Rank Beginner
Re: 1um BEOL thickness ?
Hi Max! I like your 'about 1 um'. Looking at the ITRS 2011 BEOL roadmap for MPUs (logic) Table IITC2 year 2012 (22nm node), metal 1 is 58nm thick, the intermediate metal layers (say #2 & #3) are either 115nm or 230nm (if 2X for ASICs), and global metal layers (say #4 & #5) are either 123nm or 492nm (if 4X for ASICs). Then adding it all up we get a range from 518nm to 1502nm; so 1.0+/-0.5um for the 5 layers of metal covers it. You are 'Magnificent'!
Re: 1um BEOL thickness ?
@torki: I did say that I was "rounding furiously" (grin) -- how about if we say "in the order of 1um" (double grin)
Re: Thermal could begain to be an issue at higher layer counts
@William: I agree -- heat is always a problem -- it's going to be interesting to see where this goes -- if people start using the technology in earnest then tool development will ramp up also.
Re: This is true 3D-IC integration
@Tork: "The process seems a variant of the SmartCut process from SOITEC. Are you collaborating with them?"
Nope -- I haven't even heard of them -- but I certainly would like to learn more about what they are doing (when I get a free moment).
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