JezmoSSL
8/16/2012 8:02:21 AM
User Rank Blogger
Re: programming
Equaly it is very important that you don't think of a hdl as a programming language, VHDL for example could be conciderd a simulation language of sorts, but there are many very subtle ways in which it is nothing of the kind.
An HDL is just an abstraction layer.
Re:Verilog & VHDL
@SolderJunkie: The Folks at Synapse Wireless use Python to create the application programs that run on their small wireless modules. These applications are compiled (translated) into byte code that then runs on a Python virtual machine that is running on the wireless node's microcontroller
Re: What we need is a library of short examples.
@Hamster: I know the folks at Impulse Accelerated Computing -- let me ask them to create this example -- I'm travelling on business at the moment -- remind me next week when I'm back in my office
Re:Verilog & VHDL
This section (Part 3) is a nice easy nudge towards the light switch connected to the light bulb over my head. Before now I have been half hearted in following this tech and wondering if it will pass into the ether as another toy of the month. By this I refer to Java once being seen as the replacement for C/C++ in MCU programming. Seems like a lot of time and money is being invested in development by some of the big players. This is not a guarantee of success, but very encouraging. The success may be a no brainer to a lot of you here tracking the progress , I hope to be one of you soon.
hamster
8/15/2012 2:44:00 PM
User Rank Blogger
Re: What we need is a library of short examples.
Hi Jan,
I've switched it to IEEE.NUMERIC_STD. Don't know if I did it the right way by using lots of conversion functions, but it implements.
'n' has been removed from the sensitvity list, and I've stopped using it. It was a kludge to get top raster lined up...
> what is the logic behind the "n.vCounter(9 downto 4)" checks?
Cut and paste the lines into a text editor, and replace all the 0s with spaces. The mystery will be solved.... :-)
Re: What we need is a library of short examples.
Let me start with some critique before taking up the challenge.
First, you really should not be using ieee.std_logic_unsigned. Despite appearances, it is not a standard and therefore bad practice. Use ieee.numeric_std instead.
Second: you use a combinatorial process that uses its own output back as input. Apparently you rely on a few round-trips to get the values right. Really, this is playing with fire. If the values don't stabilize, there's a nice infinite loop. To understand that it works in this case really is confusing.
When one wants to use the "future" value of a signal, that just calls for the use of a temporary variable instead of combinatorial round-trips. While we are at it, better move all the behavior into a sequential process, avoiding all kinds of nasty problems with combinational processes.
Actually, this is a perfect illustration of my principal message. As it stands, this code probably tries to stay close to "describing" hardware by using only signals and a focus on combinatorial logic. But a more abstract "software-oriented" approach would lead to clearer, more robust code without sacrificing implementation efficiency.
Finally: what is the logic behind the "n.vCounter(9 downto 4)" checks? The current sequence is 0, 2, 3, 4, 5, 6, 36 - I don't understand why.
hamster
8/15/2012 3:35:13 AM
User Rank Blogger
What we need is a library of short examples.
I rant about C to HDL translaters But I've never used one. To solve my ignorance, I would really like to see what the code looks like.
If anybody can code a small design that displays "Hello world" on a VGA screen using a C tool I'ld be really keen to see it.
Here's my VHDL attempt: http://hamsterworks.co.nz/mediawiki/index.php/Papilio_Plus/Hello_World
thrakkor
8/15/2012 12:30:01 AM
User Rank Blogger
Re: It all makes sense
I personally can't stand graphical/schematic based design (beyond good block diagrams or detailed ones for documentation only), but if that is what works for you, it is the "right" solution, especially since you only have to answer to yourself. heck i'd even prefer VHDL instead of schematics for board design.
that said, if you were to do schematic design using Xilinx components, you could not port your design to another vendor based FPGA board without redrawing everything in the new vendor tools.
Re: I believe the view presented here is flawed.
So true. I marvel that I can but a 16-bit microcontroller like the MSP430G for a dollar. For what it can do, it seems it should sell for much more, but I guess they need to more them out the door. I could never design a microcontroller, but I'm sure glad someone else can.
It all makes sense
A few years ago, I used a program called WinPlace to configure the 22CV10 SPLD. It allowed me to setup either combinational or sequential logic for about 10 outputs, while it looked at 11 inputs and a CLK pin. We used the chip as part of a digital fundamentals class after I realized that we were spending huge amounts of class time chasing down wiring errors and faulty chips. After we ran through a bunch of simple AND-OR circuits, we switched over to sequential logic, and we were ablt to create state-machines with about 8 different states. We designed sequential process controllers all without any real programming. I'm still impressed at what we were able to do. We would set the CLK rate to something around 1KHz since we were just looking at limit switches and pushbuttons.
I'm eager to attempt the same sorts of projects using the Papilio and the LX-9 board. My biggest obstacle is that of time. I'd love to have a few more hours a day, but complaining won't make it better, so it's time to dive it. I did some design work about a year ago with Xilinx ISE. I like grahical somutions, so I'm thinking of using the schematic option instead of VHDL. Is this reasonable? I'm looking at a VHDL primer, and it looks like the schematic option would be faster for me. The schematic option reminds me of function block diagram programming, in which I don't need to go into too much detail.
Somehow I'll make time this week and get one or two sequential projects hammered out. Fingers crossed.
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To celebrate Geek Pride Day, Sylvie Barak has created a mega-cool infographic that depicts how geeks have been building the Internet since 1832.
When traversing serial links with optics or backplanes, high-speed signals are degraded by impairments in the link, such as insertion loss, reflections, crosstalk, and optical dispersion.
Can statistical or heuristic verification really work for FPGA designs?
One of the things I've been wondering is whether or not the "okWireOR" module is really just a giant OR, or if the order in which things are attached matters.
I am shocked and horrified. It appears that those little scamps at Planet Analog are writing blogs pertaining to field-programmable issues.
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