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most recent messages 5/23/2013 3:43:47 AM jandecaluwe @a1js "I don't know whether a similar approach works in Verilog" I don't think so currently. I think it requires a edge check in procedural code (rising_edge) instead of the sensitivity list (sig.posedge). On... blog roll message boards chat Are You Ready for Geek Pride Day (May 25)? Max Maxfield, Editor in Chief, All Programmable Planet, 5/22/2013 Comment now 3 comments What's so special about the 25th of May? Well, first off, it's Towel Day, the day two weeks after Hitchhiker's Guide to the Galaxy author Douglas Adams passed in 2001. If you're a hoopy frood, you'll want to keep your towel handy in case you are whisked away on a starship. Most recent post, SylvieBarak, 5/22/2013 7:49:49 PM TOTALLY going to make a towel of this, Max! Wow, ever considered a career in Atmel... Implementing SerDes for FPGAs: More Challenges Warren Miller, Independent Consultant, 5/22/2013 Comment now In this blog, I'm going to update my earlier column on SerDes technology. Things are moving so fast in this area, and the area itself is so technically rich, that another miniseries of blog posts seemed appropriate. Statistical Coverage for FPGA Verification Brian Bailey, Independent Consultant, 5/22/2013 Comment now 7 comments In my previous blog relating to functional verification, I discussed the difficulties associated with ensuring complete verification without some form of measured coverage. One of the comments on that article suggested that if you ran an FPGA in the design environment for long enough, then statistically, you were likely to have exercised most of the ... Most recent post, William Murray, 5/22/2013 9:19:13 PM Just look at all the Floating Point math bugs that have made it to production in... The Opal Kelly FrontPanel: Experimenting With 'okWireOR' Modules Tom Burke, Senior Systems Engineer, 5/21/2013 Comment now 29 comments In one of my earlier columns, we figured out how to use the "okWireOR" module to combine multiple signals going from the XEM board back to the PC. (See: The Opal Kelly FrontPanel: Using Multiple WireOuts.) Most recent post, taimoortariq, 5/23/2013 12:10:57 AM @Tom your doing a great job. Because as a student, I believe providing the software... Field-Programmable Analog & GaAs – Oh My! Max Maxfield, Editor in Chief, All Programmable Planet, 5/21/2013 Comment now 10 comments Good grief. I am shocked and horrified. Someone is treading on our turf, as it were. What am I waffling on about? Well, I was just casting my orbs over one of All Programmable Planet's sister sites -- Planet Analog. As you doubtlessly know, Planet Analog is ruled by that international man of mystery, Brad Albing, he of the iron fist in the velvet glove ... Most recent post, MacChalium, 5/22/2013 5:24:13 PM Some projects may be able to tolerate those lead times and costs but Iwouldn't try... Don't Miss This Week's Live Chat! Max Maxfield, Editor in Chief, All Programmable Planet, 5/20/2013 Comment now 14 comments As always, this week's All Programmable Planet (APP) live online chat -- which will be held on Thursday, May 23 -- promises to be a rip-roaring, fun-filled, roller-coaster thrill ride of thrust-and-parry ideas. (Only thrill seekers need apply.) Most recent post, Max Maxfield, 5/22/2013 9:36:17 AM @William: Some people prefer to take a relaxed approach to FPGA design, others prefer... Discovering FPGAs: Robot + ZedBoard + Linux Duane Benson, Technical Marketing Manager, Screaming Circuits, 5/20/2013 Comment now 8 comments If you've been following my Discovering FPGAs blogs, you know that I'm the guy driving really slow in the fast lane. Most recent post, Duane Benson, 5/22/2013 3:38:48 PM That sounds like a pretty intriguing project. It would be the best of all three... A Word to the Wise Max Maxfield, Editor in Chief, All Programmable Planet, 5/17/2013 Comment now 29 comments Have you ever noticed how sometimes there seems to be an ebb and flow to the things that are happening around us? For example, it seems to me that more "wise words"-type items have been passing in front of my eyes recently than is usually the case. Most recent post, Crusty, 5/21/2013 10:09:46 AM Is it my electrons or is anyone else having difficulty seeing our beloved Max on... Adam Powers Up His Zynq ZedBoard, Part 7 Adam Taylor, Principal Hardware Engineer, Astrium, 5/17/2013 Comment now 14 comments When we left Part 6 of this epic mini-series, we had just completed the generation of the bit file containing the XADC (Xilinx Analog-to-Digital Convertor) along with the original GPIO (General-Purpose Input/Output) connected to the LEDs and the processor system. Most recent post, Tobias, 5/21/2013 2:22:54 AM JezmpSSL, let me know when you are in the alps. Let's have a bike ride. I have an... Extreme Thermal Cycling & Component Packaging William Murray, Electrical Engineer, 5/16/2013 Comment now 10 comments It is often the case that printed circuit boards (PCBs) and the components mounted on them, including the occasional FPGA, will be thermal cycled over a great temperature range several times a day, even when in operation. Most recent post, SunitaT, 5/21/2013 7:56:08 AM Is it possible to have a special chip dedicated for testing how the transistors... Ask Max: Tri-State Fundamentals, Part 3 Max Maxfield, Editor in Chief, All Programmable Planet, 5/16/2013 Comment now 13 comments In Part 1 of this mini-series we considered a three-state (tri-state) scenario in the context of an input buffer. In Part 2 we progressed to a tri-state output buffer. Now, in this column we will consider the tri-state concept in the context of the legendary bi-directional buffer, but first... Most recent post, Max Maxfield, 5/22/2013 4:30:12 PM @hw_fw_engr: I always enjoy reading your columns. Oooh -- you smooth talker you... Next 5 blogs + All blogs All blogs most commented 29 A Word to the Wise Max Maxfield, Editor in Chief, All Programmable Planet, 5/17/2013 29 The Opal Kelly FrontPanel: Experimenting With 'okWireOR' Modules Tom Burke, Senior Systems Engineer, 5/21/2013 14 Don't Miss This Week's Live Chat! Max Maxfield, Editor in Chief, All Programmable Planet, 5/20/2013 14 Adam Powers Up His Zynq ZedBoard, Part 7 Adam Taylor, Principal Hardware Engineer, Astrium, 5/17/2013 13 Operational, Differential & Instrumentation Amplifiers, Part 2 Andrew Porter, Specialist Electronics Engineer, EADS Astrium, UK, 5/16/2013 blog roll message boards chat 5/23/2013 3:43:47 AM Re: And what about MyHDL: @a1js "I don't know whether a similar approach works in Verilog" I don't think so currently. I think it requires a edge check in procedural code (rising_edge) instead of the sensitivity list (sig.posedge). On the horizon, a solution may be... jandecaluwe on A Chess-Playing FPGA: Let the Coding Begin! 5/23/2013 1:00:37 AM Re: And what about MyHDL: Gordwait, By "partial resets" in one process, I mean inferring synchronous storage elements (registers, rams, etc.) with different types of reset (or no reset) within the same clocked, VHDL process. Here is an example of a single process... aj1s on A Chess-Playing FPGA: Let the Coding Begin! 5/23/2013 12:39:16 AM Re: And what about MyHDL: Chris, Yes, one can constrain themselves to the 1:1 subset of MyHDL, but the benefits of that over native VHDL/Verilog are small, perhaps not worth the pain of dealing with yet another intermediate step, and another tool in the chain. Another... aj1s on A Chess-Playing FPGA: Let the Coding Begin! 5/23/2013 12:36:47 AM Re: Happy audience: "What are you talking about -- NOBODY gets bored during one of my presentations (grin)" Max, that's I have to check with audience (grin). It's a general statement and not meant for your audience. Myplanet on Slideshow: Max at Design West 2013 5/23/2013 12:35:00 AM Re: Design West: "we arranged to meet at 3:00pm on the Sunday outside the main registration desk and I always wear a Hawaiian shirt -- so that made it easier :-)" Max, your APP card wont worked for you. I think that's one of the main objectives, while introducing... Myplanet on Slideshow: Max at Design West 2013 5/23/2013 12:30:43 AM Re: Power Switch OFF: "Come on, there is a few men behind the DCD but saying at once billions or millions? ;)"That's the way of self satisfaction ;) I hope atleast somebody will be there !!! Myplanet on What to Look for When Selecting Third-Party IP, Part 8 5/23/2013 12:10:57 AM quite helpful: @Tom your doing a great job. Because as a student, I believe providing the software specific information is always very helpful. It broadens our know how of the functions of devices being used. And I am sure, after reading your blogg a person... taimoortariq on The Opal Kelly FrontPanel: Experimenting With 'okWireOR' Modules 5/22/2013 11:51:13 PM Re: last time I checked ...: "I was pointing to the Indian context but if you can share your thoughts on any company it too would be helpful for me" Geekyasa, I personally feel that this is not the right forum for either evaluating or for criticizing any company or products. ... Myplanet on SW Development vs. HW Engineering: Is the Race Over? 5/22/2013 9:52:06 PM Re: Useful!: Go back through my 1st couple - I explain it there, I think - how to make a symbol, that is... tomii on The Opal Kelly FrontPanel: Experimenting With 'okWireOR' Modules 5/22/2013 9:19:13 PM Re: SSA Faults for digital: Just look at all the Floating Point math bugs that have made it to production in comercial microprocessors and CPU's! (Test coverage on Math functions (100% for SSA is very difficult) William Murray on Statistical Coverage for FPGA Verification 5/22/2013 8:30:15 PM Re: And what about MyHDL: Can you guys describe what you mean by "partial resets" in one process? I'm missing some datapoint in my head.. :) GordWait on A Chess-Playing FPGA: Let the Coding Begin! 5/22/2013 8:12:45 PM Re: And what about MyHDL: Yep, that would make an async reset, since the process is sensitive to both the clock and reset inputs, and reset has higher precedence over the clock edge.. (I'm late getting back to the discussion, so forgive the "Captain obvious" feedback... GordWait on A Chess-Playing FPGA: Let the Coding Begin! Next 5 messages + All messages All messages blog roll message boards chat 5/20/2013 4:25:23 PM 23 May 2013 Live Chat: Our weekly chat will commence at 12:00 p.m. my time (Central USA Time), which is 1:00 p.m. Eastern Time, 10:00 a.m. Pacific Time, and 6:00pm GMT/UTC. You'll have to work out your local time from these clues (of course you can always use this... Max Maxfield Blogger 5/16/2013 2:08:45 PM 16 May 2013 Live Chat: @Max: That cookies seem like the ultime cholesterol festival -- I'll try to cook my own version!! Garcia-Lasheras Blogger 5/16/2013 2:07:49 PM 16 May 2013 Live Chat: OK -- I have to go too -- I've got to finish off my Tri-State logic part 3 blog -- C U all next week Max Maxfield Blogger 5/16/2013 2:07:38 PM 16 May 2013 Live Chat: @Robin: I'll tell you when I get to taste them Max Maxfield Blogger 5/16/2013 2:06:58 PM 16 May 2013 Live Chat: @Max, re chocolate/bacon cookies. Oh yeah... Two of my favorite things. Really curious if it's a good combo though... not sure. rfindley Blogger 5/16/2013 2:05:59 PM 16 May 2013 Live Chat: I've got to go too. Good chatting Duane Benson Blogger 5/16/2013 2:05:48 PM 16 May 2013 Live Chat: Hey -- I just remembered -- did you see my blog on Chocolate Chip Bacon Cookies Max Maxfield Blogger 5/16/2013 2:05:35 PM 16 May 2013 Live Chat: @All- got to go. thanx for the chat! Warren Miller Blogger 5/16/2013 2:05:08 PM 16 May 2013 Live Chat: @Max: Thaks, I'll will search that after dinner!! -- 20:00 in Spain now! Garcia-Lasheras Blogger 5/16/2013 2:04:38 PM 16 May 2013 Live Chat: Sweet! rfindley Blogger Next 5 chats +		flash poll All polls information resources sponsored content by Xilinx Xcell Journal Issue 83 Xilinx Smarter Networks Backgrounder Video: Smarter Solutions for Packet Processing Video: Smarter Solutions for Optical Transport Networking Video: Smarter Solutions for Software Defined Networking Video: Smarter Solutions for Data Centers All Programmable FPGAs and SoCs for Fast, Cost-Effective Designs - December 10 -14 Noon EST Sponsored by Xilinx User Guide - Zynq-7000 All Programmable SoC Technical Reference Manual User Guide Zynq-7000 All Programmable SoC PCB Design and Pin Planning Guide Kintex-7 FPGA Connectivity Targeted Reference Design User Guide All resources follow us on twitter Follow us follow Xilinx on twitter Follow us like us on facebook like Xilinx on facebook

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